[Under construction]2016 AFOSR MURIPO: Dr. Gernot Pomrenke, Optoelectronics and PhotonicsPI: Ray Chen, University of Texas at AustinMURI Website
Even if the continuation of Moore's law meets a bottleneck, the increasing trend of network connections and bandwidth consumed is accelerating with no foreseeable sign of halting because of the bandwidth-hungry applications. The total amount of content passing through the world’s networks is expected to increase to 35 Zettabytes（1021）with unprecedented power consumption by 2020, meaning that by the end of this decade, with current technologies, service providers will need an astonishing over 20 times of power consumption they have in 2015.
Optoelectronic interconnects and optical logic gates provide key solutions to drastically reduce the power to modulate (e-to-o conversion), processing, transport, and demodulate (o-to-e) high speed signals with power consumption down to attojoule/bit (AJ/B) level. In this program, we propose a myriad of ultra-low power nanooptoelectronic devices for intra- and inter-chip optical interconnects and computing. A vertical cavity surface emitting nano-lasers is proposed with high injection current confinement and extremely high quantum efficiency that can provide 1 to 2 orders magnitude power saving to 100 Gbit/sec. A modified uni-traveling carrier (MUTC) photo receiver is also proposed to solely utilize highly mobile electrons to provide o-to-e conversion with near-to-unity quantum efficiency at zero bias that can be integrated on a silicon photonics platform. An innovative modulator using the combination of the slow light effect on Si photonic crystal and the plasmonic free carrier absorption effect drastically reduces the device size and modulation efficiency to <100 AttoJoule/Bit level at above 25 Gbit/sec, which is at least one order of magnitude less than the state-of-the art devices. To provide wavelength routing in a WDM (wavelength division multiplexing) based on-chip network, a low power nxn wavelength router is proposed using 2D photonic crystal based slow light effect with great power saving capability.
To further solve the problem in huge power consumption of the state-of the art data centers and cloud computing, we propose to take advantage of the optical computing and design an extreme adder architecture suitable for ultra-high bit count (such as 256, 512, 1024-bit). Our proposed nbit full adder are full implementable on a silicon platform using guided wave optics. Note that all the basic digital logic functions can be realized employing optical logic devices without energy consumption (0 joule/bit) while the calculation is being performed. Energy is only expended when the final result is being extracted. In electronics, energy is dissipated at each step along the calculation path. Another tremendous advantage over the conventional electronic scheme is the elimination of gate latency and simultaneous availability of a logic function and its complementary at the output, which makes the approach proposed herein extremely efficient. The proposed device implementation for a 256 bit carry-ripple adder is capable of providing two orders of magnitude power saving and one order magnitude of latency reduction (and therefore one order of magnitude faster in computing speed) when compared to the electronic counter parts. Mid-IR nanooptoelectronics platform is also proposed to provide low power solution with better performance for free space communications and sensing.
The success of this program will significantly improve the power consumption and computation speed for USAF/DOD computing/signal processing and sensing platforms to better defend our country. The basic science advancements proposed herein are dual-use in nature which can also benefit civilian sectors significantly.